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APLL

VeriSilicon Microelectronics

This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO of this PLL can run up to 1000MHz. It contains a 1-64 input clock divider, a 1-128 feedback clock divider and a 1-8 output clock divider. By setting PLL_DM, PLL_DN and PLL_DP to different values, the output clock will be locked at different multiples of the input frequency.

  • Process: GLOBALFOUNDRIES 0.13um 1.2v 1P6M/7M/8M CMOS logic process
  • Supply voltage: 1.08V~1.2V~1.32V
  • Current: <2.5mA
  • Operating junction temperature: - 40°C ~ +25°C ~ +125°C
  • Core area: 541.73um x 438.75um
  • Two outputs: - PLL_CLKO: standard output from the output divider - PLL_CLK: output from VCO directly

Summary

Catalog ID

GF13V33_PLL_07

IP Provider

Vendor

Designer

VeriSilicon Microelectronics

Type

Soft IP

Node

130nm

Vendor

VeriSilicon Microelectronics

Foundry

GlobalFoundries

Process

GF013

Category

Oscillator and Clocking

Certifications

icon

Licensing

Info

Contact Designer

Maturity

Stage

product

# of Tries

1

Library Package

Version

1.0

Version Date

May 27, 2014